# NFC Antenna Multiplexer Module — Design Brief

## Project overview

I'm building an automated chess board that detects which piece is on which square using NFC. Each chess piece has an NTAG213/215 sticker on its base. The board is divided into **12 identical modules**, each covering **8 squares** (2 columns x 4 rows). All 12 modules together form the full 8x8 = 64-square board.

**This brief describes one module.** I need a professional review of the attached design files (KiCad PCB, Gerbers, BOM, CPL) before ordering from JLCPCB with full PCBA assembly.

---

## What this module does

A single PN532 NFC reader (external, not on this board) scans 8 antennas one at a time through an analog multiplexer. The Raspberry Pi 4B selects which antenna is active by driving 3 address lines (S0, S1, S2) and an enable line (EN). The mux routes the selected antenna's signal to a common output (Z/COM) which connects to the PN532's antenna port.

**Signal chain:** PN532 ANT → wire → J1 header → mux Z/COM (pin 9) → selected I_x channel → via → spiral antenna on PCB → 0R bridge → GND return

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## Board specifications

| Parameter | Value |
|---|---|
| Dimensions | 80 x 185 mm |
| Layers | 2 (F.Cu + B.Cu) |
| Material | FR-4, 1.6mm |
| Copper weight | 1 oz (35 um) |
| Surface finish | HASL or ENIG |
| Min trace/space | 0.25 / 0.25 mm |
| Min drill | 0.3 mm |
| Solder mask | Both sides |
| Silkscreen | Front only |

---

## Components (BOM)

| Ref | Value | Package | Function | LCSC# |
|---|---|---|---|---|
| U1 | CD74HC4067E | DIP-24 (7.62mm socket) | 16:1 analog mux (only 8 channels used) | C149147 |
| C1 | 120 pF | 0603 | Tuning cap — resonates antenna at 13.56 MHz | C1653 |
| C2 | 100 nF | 0603 | VCC decoupling cap for U1 | C14663 |
| R1–R8 | 0 ohm | 0603 | Bridge jumpers — connect each antenna's outer end to GND | C17168 |
| J1 | 1x7 pin header | 2.54mm vertical THT | Connector to RPi/PN532 | C124378 |

**Total: 13 components** (1 IC + 2 caps + 8 resistors + 1 header)

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## CD74HC4067E pinout (DIP-24) — CRITICAL

This is the pin assignment we are using. Please verify against the TI datasheet for the CD74HC4067E N package (DIP-24):

```
              CD74HC4067E  DIP-24
              ┌────────U────────┐
   Pin 1  I7  │ 1            24 │  VCC (3.3V)
   Pin 2  I6  │ 2            23 │  I8  (unused)
   Pin 3  I5  │ 3            22 │  I9  (unused)
   Pin 4  I4  │ 4            21 │  I10 (unused)
   Pin 5  I3  │ 5            20 │  I11 (unused)
   Pin 6  I2  │ 6            19 │  I12 (unused)
   Pin 7  I1  │ 7            18 │  I13 (unused)
   Pin 8  I0  │ 8            17 │  I14 (unused)
   Pin 9  Z   │ 9            16 │  I15 (unused)
   Pin 10 S0  │10            15 │  EN  (active low)
   Pin 11 S1  │11            14 │  S2
   Pin 12 GND │12            13 │  S3 → GND
              └─────────────────┘
```

**Key connections:**
- **Pin 9 (Z/COM)** = ANT_OUT — this is the common antenna signal going to PN532
- **Pin 13 (S3)** = tied to GND (we only use I0–I7, so the high address bit must be 0)
- **Pin 15 (EN)** = active-low enable from RPi GPIO
- **Pins 10, 11, 14** = S0, S1, S2 address lines from RPi GPIO
- **Pins 16–23** (I8–I15) = unused, left floating (is this OK? or should they be tied to GND?)

---

## Antenna design

Each of the 8 antennas is a **planar square spiral** etched on **F.Cu (front copper)**:

| Parameter | Value |
|---|---|
| Outer dimension | 25 x 25 mm |
| Number of turns | 5 |
| Trace width | 0.25 mm |
| Trace gap | 0.25 mm |
| Inner opening | 20.5 x 20.5 mm |
| Calculated inductance | 1.094 uH (Wheeler formula) |
| Target frequency | 13.56 MHz |
| Ideal tuning cap | 126 pF |
| Actual tuning cap (C1) | 120 pF (nearest standard value) |
| Actual resonant frequency | ~13.9 MHz |

**Layout:** 2 columns x 4 rows, 40mm pitch (center-to-center). Each antenna sits inside a 40x40mm cell. The antenna area starts 25mm from the top edge (below the component strip).

**GND return path:** Each antenna's outer end connects through a 0-ohm 0603 resistor (R1–R8) to GND. The inner end connects via a plated through-hole via to B.Cu, where it is routed to the corresponding mux channel pin.

**B.Cu ground plane:** The entire back copper layer is a GND fill zone, **except** under each antenna where 27x27mm keepout rectangles prevent the ground plane from creating eddy currents that would reduce antenna inductance.

---

## J1 header pinout (1x7, 2.54mm pitch)

| Pin | Signal | Description |
|---|---|---|
| 1 | ANT_OUT | Analog antenna signal to/from PN532 |
| 2 | GND | Ground reference |
| 3 | S0 | Mux address bit 0 (3.3V logic) |
| 4 | S1 | Mux address bit 1 |
| 5 | S2 | Mux address bit 2 |
| 6 | EN | Mux enable (active LOW) |
| 7 | VCC | 3.3V power supply |

---

## Routing summary

- **F.Cu:** Spiral antennas, short stub traces (C1→pin 9, C2→pin 24), GND stubs from R pads to vias
- **B.Cu:** Signal routing from antenna inner vias to DIP-24 pins (L-shaped paths), GND fill zone with antenna keepouts
- **Signal trace width:** 0.25 mm
- **GND trace width:** 0.3–0.5 mm
- **Via diameter:** 0.6 mm, drill 0.3 mm

---

## Specific questions for the reviewer

1. **Tuning cap value:** We use 120 pF for an antenna with L = 1.094 uH. This gives ~13.9 MHz instead of exactly 13.56 MHz. The PN532 has some frequency tolerance, but is this close enough? Should we use 130 pF or 150 pF instead? Or add a trimmer capacitor option?

2. **Unused mux channels (I8–I15, pins 16–23):** Currently left floating. Should they be tied to GND or left open? The TI datasheet recommends tying unused inputs to VCC or GND — which is better for an analog mux carrying RF signals?

3. **0-ohm resistors as GND bridges:** We use 0R 0603 resistors to bridge each antenna's outer trace from F.Cu to a GND via on B.Cu. Is this the right approach, or should we use direct vias instead? The 0R resistors were chosen because the antenna trace and GND pad are on opposite sides of the spiral.

4. **Single tuning cap for 8 antennas:** C1 (120 pF) sits between Z/COM (pin 9) and GND. This means the tuning capacitance is shared across all 8 antennas through the mux's on-resistance (~70 ohm typical). Is this acceptable, or should each antenna have its own tuning cap?

5. **GND plane keepouts:** The 27x27mm keepout zones under each 25mm antenna leave ~1mm margin. Is this sufficient to prevent eddy current losses, or should the keepouts be larger?

6. **S3 grounding via zone flood:** Pin 13 (S3) is set to GND net and connects through the PTH pad barrel to the B.Cu GND zone fill. There is no dedicated F.Cu trace to GND — the connection relies entirely on the plated through-hole and zone flood. Is this robust enough for manufacturing?

7. **Overall: will this work?** Given the signal chain (PN532 → mux → spiral antenna → NFC tag at ~3–5mm distance through 3mm plywood), do you see any fundamental issues with the approach?

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## Attached files

- `chess-nfc-2x4-module-v5.zip` — Gerber files (9 files: F.Cu, B.Cu, F.Mask, B.Mask, F.Silkscreen, B.Silkscreen, Edge.Cuts, drill, job)
- `chess-nfc-2x4-module-v5-BOM.csv` — Bill of Materials with LCSC part numbers
- `chess-nfc-2x4-module-v5-CPL.csv` — Component Placement List (pick-and-place positions)
- `chess-nfc-mod-v5.kicad_pcb` — KiCad PCB source file
- `chess-nfc-2x4-module-v5-top.png` — 3D render (top view)
- `chess-nfc-2x4-module-v5-bot.png` — 3D render (bottom view)
- `chess-nfc-2x4-module-v5-diagram.svg` — Schematic diagram

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## Manufacturing target

- **Manufacturer:** JLCPCB
- **Service:** PCB + PCBA (full assembly, SMD + THT)
- **Quantity:** 5 boards (minimum order)
- **Assembly side:** Top only
- **All components from LCSC** (JLCPCB's parts library)